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Sealing Cache: World’s Smallest SRAM Cell Created
Traditionally, the SRAM memory array in processors occupies a decent area (as a rule, for the first three levels of cache memory). It is difficult to reduce it since each SRAM cell contains up to six transistors. SRAM needs to be as efficient as possible and therefore relies on logic rather than capacitor charge like conventional DRAM. All this also creates problems with the scaling of the SRAM cell when moving to smaller technological norms of production. New technical processes, by the way, always start testing with the release of SRAM arrays. If this works out, then they move on to an experimental release of processor logic.
Computer and real representation of vertical transistor channels-columns and comparative areas of SRAM cells from different manufacturers (Imec)
Samsung could boast of the smallest SRAM cell to date. By this parameter, it overtook Intel. As we reported, Samsung has introduced a 6-transistor SRAM cell with an area of 0.026 μm2. For the production of a 256-Mbit experimental memory array, the Samsung 7LPP 7-nm process technology was used with partial use of EUV scanners. In a few months, this process technology will be launched on a commercial scale. Belgian development center Imec and startup Unisantis managed to release an even smaller SRAM cell. Don’t be confused by the mention of a startup. The chief technologist and director of Unisantis is the inventor of the NAND flash, Fujio Masuoka. At one time, he even received an award at the European level of the Economist Awards for this.
Unisantis and Imec create a 6-transistor SRAM cell structure no larger than 0.0205 μm2. For this, the developers abandoned horizontal transistor structures of the FinFET type (vertical channel edges surrounded by gates on three sides) and created vertical transistor channels in the form of columns, completely surrounded by gates (SGT, Surrounding Gate Transistor). This is a variety of GAA (Gate-All-Around) gates. Samsung, for example, will start using similar shutters in 2021 when it moves to 3nm process technology. Imec and Unisantis Develop SGT Technology for 5nm SRAM. Simply put, partners are proposing to start compacting SRAM in a year or two.
Experimental SGT structures with a minimum step of 50 nm for each column-channel (Imec)
The transition from horizontal structures to vertical columns of transistor channels will reduce the area of SRAM arrays by 20-30%. The sample shown, for example, showed a 24% reduction in array area. If EUV lithography is used for the production of columnar SRAM, then due to the reduction of plate processing cycles, the cost of production of vertical channels will be the same as for FinFET channels. At the same time, vertical SGT channels will provide lower current leakage and better stability of transistor parameters, as well as eliminate the problem of further downscaling. The only drawback of SGT structures can be considered their insufficient performance for use in logic gates (in terms of current characteristics, SGT is about three times worse than FinFET). But this does not prevent SGT structures from being ideally suited for the production of DRAM, SRAM and NAND.