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The transistor density in the 5nm Apple A14 is much lower than TSMC claims, but no one is to blame
ICmasters peek under the packaging of the Apple A14 Bionic processor. The crystal size is now known, and it is 88 mm2. Despite the impressive 11.8 billion transistors in the chip, the die size is incredibly small thanks to TSMC’s 5nm process. But not everything is so simple.
Apple SoCs have achieved over 90% theoretical process density in the past. The performance of this generation is much lower: the real density of transistors in the A14 is 78% compared to the theoretical. Despite TSMC claiming a 1.8x die cut for the 5nm N5 compared to the N7, Apple only achieved 1.49x the previous generation in this metric.
And this is not a failure of TSMC or Apple. Both companies are recognized leaders respectively in the production and development of semiconductor chips. The problem with the inability to convert the theoretical density to the effective density is due to the slow stopping of SRAM scaling. SRAM is widely used in processors: both for registers and for cache. TSMC’s Geoffrey Yeap claims that this typical mobile SoC today is 60% logic, 30% SRAM and 10% analog I / O.
TSMC N5 workflow differs from previous regulations showing signs of SRAM scaling slow. If the logic can be condensed 1.8 times, then for SRAM this figure was only 1.35 times. And even this figure is overestimated: in the end it will be even less when other auxiliary schemes are taken into account. SemiAnalysis believes this trend will continue with new semiconductor regulations.
TSMC and Samsung have already demonstrated 3D SRAM layering to address the density problem, but this technology is more expensive. Cost scaling slows down dramatically. Considering that the price of TSMC N5 silicon wafers is already about $ 17 thousand per one, it is clear that the cost of transistors has not dropped. Even if the SRAM scaling continued, the transistor cost would still remain unchanged from N7 to N5.