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TSMC has a fast and efficient interface for combining several crystals into one processor
Interfaces are becoming a critical part of multi-chip solutions in a single package. Once the chips are spaced across the substrate, the buses connecting them should have the highest possible bandwidth, minimum latency, and low power consumption. Today there are a dozen of such open and proprietary interfaces. And the most original of them, perhaps, was offered by Global Unichip Corp, behind which is TSMC.
GLink test board and engineering sample
Many of the interfaces for multichip packages use SerDes converters as the edge gate of the bus. This is an invariable element of almost all classical interfaces, converting a parallel data set in sequence for transmission over a limited set of lines and doing the reverse conversion at the other (receiving) end of the lines.
Global Unichip Corp (GUC) proposes to abandon SerDes as obsolete. Instead, GUC offers its own GLink interface (GUC multi-die interLink), and TSMC is prepared to embed GLink on customer orders in multi-chip packages of high-performance chips, for example, in SoC for flagship smartphones and not only.
TSMC has practiced and is ready to provide simulations of the use of the GLink interface for multi-chip packages such as InFO_oS and CoWoS for 7nm crystals. GLink is claimed to be more advantageous for these TSMC packages with multiple crystals up to 2500mm2. The new interface provides error-free communication between crystals in a package in full duplex mode with a bandwidth of 0.7 Tbit / s per mm of interface. At the same time, consumption is only 0.25 pJ / bit (0.25 W per 1 Tbit / s in full duplex mode).
According to the results obtained, GLink’s power consumption for every 10 Tbit / s of full-duplex traffic is 15-20 W lower than in the case of using SerDes. This is mainly due to the fact that SerDes have a constant consumption value regardless of traffic, and GLink consumption depends on the amount of transmitted data. Therefore, on average, under normal loads, replacing GLink with SerDes for connecting crystals in packages promises impressive energy savings – up to 20 times.
Two Advanced Methods for Multi-Chip Packaging by TSMC
Finally, GLink has developed and is preparing a GLink interface licensing package for TSMC’s 5nm process and future 3nm. In the first case, the exchange rate will increase to 1.3 Tbit / s per 1 mm of the interface, and in the second – up to 2.7 Tbit / s, and all this without increasing the consumption for transferring each bit of data. Solutions for 5- and 3-nm process technology will be available next year.
In connection with the proposal to abandon the usual SerDes for the sake of GLink, I would like to say that now is the time to abandon the usual. ASICs and special chips for machine learning and AI are spreading at a tremendous speed. Compared to classic processors, they are just as unusual and make you think in a new way and work in a new way. And this, if you think about it, is just wonderful. The computing industry has long been morally stagnant. She lacked a good kick for a long time.